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description the a3967 is a complete microstepping motor driver with built- in translator. it is designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes, with output drive capability of 30 v and 750 ma. the a3967 includes a fixed off-time current regulator that has the ability to operate in slow, fast, or mixed current-decay modes. this current-decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. the translator is the key to the easy implementation of the a3967. by simply inputting one pulse on the step input the motor will take one step (full, half, quarter, or eighth depending on two logic inputs). there are no phase-sequence tables, high- frequency control lines, or complex interfaces to program. the a3967 interface is an ideal fit for applications where a complex p is unavailable or over-burdened. internal circuit protection includes thermal shutdown with hysteresis, under-voltage lockout (uvlo) and crossover- current protection. special power-up sequencing is not required. the a3967 is supplied in a 24-pin soic, which is lead (pb) free with 100% matte tin leadframe plating. four pins are fused internally for enhanced thermal dissipation. the pins are at ground potential and need no insulation. 26184.24h features and benefits ? 750 ma, 30 v output rating ? satlington? sink drivers ? automatic current-decay mode detection/selection ? 3.0 to 5.5 v logic supply voltage range ? mixed, fast, and slow current-decay modes ? internal uvlo and thermal shutdown circuitry ? crossover-current protection microstepping driver with translator package: 24-pin soic with internally fused pins (suffix lb) functional block diagram not to scale a3967 19 18 sense 1 v bb1 v bb2 out 1a out 1b out 2a out 2b sense 2 5 9 20 16 21 17 8 4 translator load supply dwg. fp-050-3a pwm timer pwm timer pwm latch blanking mixed decay control logic uvlo and fault detect dac +- +- dac sense pwm latch blanking mixed decay 3 3 ref logic supply v cc step dir ms 1 sleep ms 2 enable rc 1 reset pfd rc 2 ref. supply v pf 8 14 1 23 10 11 22 12 13 3 15 24 2 7 6
microstepping driver with translator a3967 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com selection guide part number packing package A3967SLBTR-T 24-pin soic with internally fused pins 1000 per reel absolute maximum ratings characteristic symbol notes rating units load supply voltage v bb 30 v logic supply voltage v cc 7.0 v logic input voltage range v in t w > 30 ns ?0.3 to 7.0 v t w < 30 ns ?1 to 7.0 v sense voltage v sense 0.68 v reference voltage v ref v cc ma output current i out output current rating may be limited by duty cycle, am- bient temperature, and heat sinking. under any set of conditions, do not exceed the speci ed current rating or a junction temperature of 150 c. continuous 750 ma peak 850 ma package power dissipation p d see graph ?? operating ambient temperature t a range s ?20 to 85 oc maximum junction temperature t j (max) fault conditions that produce excessive junction temperature will activate the device?s thermal shutdown circuitry. these conditions can be toler- ated but should be avoided. 150 oc storage temperature t stg ?55 to 150 oc 50 75 100 125 150 5 1 0 allowable package power dissipation (w) temperature in o c 4 3 2 25 r = 6.0 o c/w q jt q r = 50c/w ja q r = 35c/w ja thermal characteristics characteristic symbol test conditions* value units package thermal resistance, junction to ambient r ja 2-layer pcb, 1.3 in. 2 2-oz. exposed copper 50 oc/w 4-layer pcb, based on jedec standard 35 oc/w *additional thermal information available on allegro website.
microstepping driver with translator a3967 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics at t a = +25c, v bb = 30 v, v cc = 3.0 v to 5.5v (unless otherwise noted) limits characteristic symbol test conditions min. typ. max. units output drivers load supply voltage range v bb operating 4.75 ? 30 v during sleep mode 0 ? 30 v output leakage current i cex v out = v bb ? <1.0 20 a v out = 0 v ? <-1.0 -20 a output saturation voltage v ce(sat) source driver, i out = -750 ma ? 1.9 2.1 v source driver, i out = -400 ma ? 1.7 2.0 v sink driver, i out = 750 ma ? 0.65 1.3 v sink driver, i out = 400 ma ? 0.21 0.5 v clamp diode forward voltage v f i f = 750 ma ? 1.4 1.6 v i f = 400 ma ? 1.1 1.4 v motor supply current i bb outputs enabled ? ? 5.0 ma reset high ? ? 200 a sleep mode ? ? 20 a control logic logic supply voltage range v cc operating 3.0 5.0 5.5 v logic input voltage v in(1) 0.7v cc ? ? v v in(0) ? ? 0.3v cc v logic input current i in(1) v in = 0.7v cc -20 <1.0 20 a i in(0) v in = 0.3v cc -20 <1.0 20 a maximum step frequency f step 500* ? ? khz blank time t blank r t = 56 k , c t = 680 pf 700 950 1200 ns fixed off time t off r t = 56 k , c t = 680 pf 30 38 46 s continued next page ? table 1. microstep resolution truth table ms1 ms2 resolution l l full step (2 phase) h l half step l h quarter step h h eighth step
microstepping driver with translator a3967 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics (continued) at t a = +25c, v bb = 30 v, v cc = 3.0 v to 5.5v (unless otherwise noted) characteristic symbol test conditions limits min. typ. max. units control logic (cont?d) mixed decay trip point pfdh ? 0.6v cc ?v pfdl ? 0.21v cc ?v ref. input voltage range v ref operating 1.0 ? v cc v reference input impedance z ref 120 160 200 k gain (g m ) error (note 3) e g v ref = 2 v, phase current = 38.37% ? ? ? 10 % v ref = 2 v, phase current = 70.71% ? ? ? 5.0 % v ref = 2 v, phase current = 100.00% ? ? ? 5.0 % thermal shutdown temp. t j ? 165 ? c thermal shutdown hysteresis ? t j ?15?c uvlo enable threshold v uvlo increasing v cc 2.45 2.7 2.95 v uvlo hysteresis ? v uvlo 0.05 0.10 ? v logic supply current i cc outputs enabled ? 50 65 ma outputs off ? ? 9.0 ma sleep mode ? ? 20 a * operation at a step frequency greater than the speci ed minimum value is possible but not warranteed. ? 8 microstep/step operation. notes: 1. typical data is for design information only. 2. negative current is de ned as coming out of (sourcing) the speci ed device terminal. 3. e g = ([v ref /8] ? v sense )/(v ref /8)
microstepping driver with translator a3967 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com device operation. the a3967 is a complete microstep- ping motor driver with built in translator for easy operation with minimal control lines. it is designed to operate bipolar stepper motors in full-, half-, quarter- and eighth-step modes. the current in each of the two output full bridges is regulated with xed off time pulse-width modulated (pwm) control circuitry. the full-bridge current at each step is set by the value of an external current sense resis- tor (r s ), a reference voltage (v ref ), and the dacs output voltage controlled by the output of the translator. at power up, or reset, the translator sets the dacs and phase current polarity to initial home state (see gures for home-state conditions), and sets the current regulator for both phases to mixed-decay mode. when a step command signal occurs on the step input the translator automati- cally sequences the dacs to the next level (see table 2 for the current level sequence and current polarity). the mic- rostep resolution is set by inputs ms 1 and ms 2 as shown in table 1. if the new dac output level is lower than the pre- vious level the decay mode for that full bridge will be set by the pfd input (fast, slow or mixed decay). if the new dac level is higher or equal to the previous level then the decay mode for that full bridge will be slow decay. this automatic current-decay selection will improve microstep- ping performance by reducing the distortion of the current waveform due to the motor bemf. reset input (reset). the reset input (active low) sets the translator to a prede ned home state (see gures for home state conditions) and turns off all of the outputs. step inputs are ignored until the reset input goes high. step input (step). a low-to-high transition on the step input sequences the translator and advances the motor one increment. the translator controls the input to the dacs and the direction of current ow in each wind- ing. the size of the increment is determined by the state of inputs ms 1 and ms 2 (see table 1). microstep select (ms 1 and ms 2 ). input terminals ms1 and ms 2 select the microstepping format per table 1. changes to these inputs do not take effect until the step command (see gure). direction input (dir). the state of the direction input will determine the direction of rotation of the motor. internal pwm current control. each full bridge is controlled by a xed off-time pwm current-control cir- cuit that limits the load current to a desired value (i trip ). initially, a diagonal pair of source and sink outputs are enabled and current ows through the motor winding and r s . when the voltage across the current-sense resistor equals the dac output voltage, the current-sense compara- tor resets the pwm latch, which turns off the source driver (slow-decay mode) or the sink and source drivers (fast- or mixed-decay modes). the maximum value of current limiting is set by the selection of r s and the voltage at the v ref input with a transconductance function approximated by: i trip max = v ref /8r s the dac output reduces the v ref output to the cur- rent-sense comparator in precise steps (see table 2 for % i trip max at each step). i trip = (% i trip max/100) x i trip max fixed off-time. the internal pwm current-control circuitry uses a one shot to control the time the driver(s) remain(s) off. the one shot off-time, t off , is determined by the selection of an external resistor (r t ) and capacitor (c t ) connected from the rc timing terminal to ground. the off time, over a range of values of c t = 470 pf to 1500 pf and r t = 12 k to 100 k is approximated by: t off = r t c t functional description
microstepping driver with translator a3967 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com rc blanking. in addition to the xed off-time of the pwm control circuit, the c t component sets the compara- tor blanking time. this function blanks the output of the current-sense comparator when the outputs are switched by the internal current-control circuitry. the comparator out- put is blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, and/or switching transients related to the capacitance of the load. the blank time t blank can be approximated by: t blank = 1400c t enable input (enable). this active-low input enables all of the outputs. when logic high the outputs are dis- abled. inputs to the translator (step, direction, ms 1 , ms 2 ) are all active independent of the enable input state. shutdown. in the event of a fault (excessive junction temperature) the outputs of the device are disabled until the fault condition is removed. at power up, and in the event of low v cc , the under-voltage lockout (uvlo) circuit disables the drivers and resets the translator to the home state. sleep mode (sleep). an active-low control input used to minimize power consumption when not in use. this dis- ables much of the internal circuitry including the outputs. a logic high allows normal operation and startup of the device in the home position. percent fast decay input (pfd). when a step input signal commands a lower output current from the previous step, it switches the output current decay to either slow-, fast-, or mixed-decay depending on the voltage level at the pfd input. if the voltage at the pfd input is greater than 0.6v cc then slow-decay mode is selected. if the voltage on the pfd input is less than 0.21v cc then fast-decay mode is selected. mixed decay is between these two levels. mixed decay operation. if the voltage on the pfd in- put is between 0.6v cc and 0.21v cc , the bridge will oper- ate in mixed-decay mode depending on the step sequence (see gures). as the trip point is reached, the device will go into fast-decay mode until the voltage on the rc termi- nal decays to the voltage applied to the pfd terminal. the time that the device operates in fast decay is approximated by: t fd = r t c t in (0.6v cc /v pfd ) after this fast decay portion, t fd , the device will switch to slow-decay mode for the remainder of the xed off-time period. functional description (cont?d) typical output saturation voltages show- ing satlington sink-driver operation. 200 dwg. gp-064-1a 0 0 7 0 0 4 300 output current in milliamperes 2.0 output saturation voltage in volts 1.0 0 0.5 1.5 2.5 500 600 t a = +25 c source driver sink driver
microstepping driver with translator a3967 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com timing requirements (t a = +25c, v cc = 5 v, logic levels are v cc and ground) a. minimum command active time before step pulse (data set-up time) ..... 200 ns b. minimum command active time after step pulse (data hold time) ........... 200 ns c. minimum step pulse width ...................... 1.0 s d. minimum step low time ......................... 1.0 s e. maximum wake-up time ......................... 1.0 ms a b c d 50% step ms1/ms2/ dir/reset dwg. wp-042 sleep e
microstepping driver with translator a3967 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com layout. the printed wiring board should use a heavy ground plane. for optimum electrical and thermal performance, the driver should be soldered directly onto the board. the load supply terminal, v bb , should be decoupled with an electrolytic capacitor (>47 f is recommended) placed as close to the device as possible. to avoid problems due to capacitive coupling of the high dv/dt switching transients, route the bridge-output traces away from the sensitive logic-input traces. always drive the logic inputs with a low source impedance to increase noise immunity. grounding. a star ground system located close to the driver is recommended. the 24-lead soic has the analog ground and the power ground internally bonded to the power tabs of the package (leads 6, 7, 18, and 19). applications information current sensing. to minimize inaccuracies caused by ground-trace ir drops in sensing the output current level, the current-sense resistor (r s ) should have an indepen- dent ground return to the star ground of the device. this path should be as short as possible. for low-value sense resistors the ir drops in the printed wiring board sense resistor?s traces can be signi cant and should be taken into account. the use of sockets should be avoided as they can introduce variation in r s due to their contact resistance. allegro microsystems recommends a value of r s given by r s = 0.5/i trip max thermal protection. circuitry turns off all drivers when the junction temperature reaches 165c, typically. it is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. thermal shutdown has a hysteresis of approximately 15c.
microstepping driver with translator a3967 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com full step half step ? step step phase 1 current (%i trip max) (%) phase 2 current (%i trip max) (%) step angle (o) 1 1 1 100.00 0.00 0.0 2 98.08 19.51 11.3 2 3 92.39 38.27 22.5 4 83.15 55.56 33.8 1 2 3 5 70.71 70.71 45.0 6 55.56 83.15 56.3 4 7 38.27 92.39 67.5 8 19.51 98.08 78.8 3 5 9 0.00 100.00 90.0 10 C19.51 98.08 101.3 6 11 C38.27 92.39 112.5 12 C55.56 83.15 123.8 2 4 7 13 C70.71 70.71 135.0 14 C83.15 55.56 146.3 8 15 C92.39 38.27 157.5 16 C98.08 19.51 168.8 5 9 17 C100.00 0.00 180.0 18 C98.08 C19.51 191.3 10 19 C92.39 C38.27 202.5 20 C83.15 C55.56 213.8 3 6 11 21 C70.71 C70.71 225.0 22 C55.56 C83.15 236.3 12 23 C38.27 C92.39 247.5 24 C19.51 C98.08 258.8 7 13 25 0.00 C100.00 270.0 26 19.51 C98.08 281.3 14 27 38.27 C92.39 292.5 28 55.56 C83.15 303.8 4 8 15 29 70.71 C70.71 315.0 30 83.15 C55.56 326.3 16 31 92.39 C38.27 337.5 32 98.08 C19.51 348.8 table 2. step sequencing home state = 45o step angle, dir = h
microstepping driver with translator a3967 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com dwg. wk-004-19 phase 1 current phase 2 current step input slow decay 70.7% ?70.7% 70.7% ?70.7% slow decay full step operation ms 1 = ms 2 = l, dir = h the vector addition of the output currents at any step is 100%.
microstepping driver with translator a3967 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com dwg. wk-004-18 phase 1 current phase 2 current step input slow decay mixed decay slow decay mixed decay 100% ?100% 100% ?100% slow decay mixed decay slow decay mixed decay slow decay mixed decay slow decay mixed decay slow decay mixed decay slow decay mixed decay 70.7% ?70.7% 70.7% ? 70.7% half step operation ms 1 = h, ms 2 = l, dir = h the mixed-decay mode is controlled by the percent fast decay voltage (v pfd ). if the volt- age at the pfd input is greater than 0.6v cc then slow-decay mode is selected. if the volt- age on the pfd input is less than 0.21v cc then fast-decay mode is selected. mixed decay is between these two levels.
microstepping driver with translator a3967 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com quarter step operation ms 1 = l, ms 2 = h, dir = h the mixed-decay mode is controlled by the percent fast decay voltage (v pfd ). if the voltage at the pfd input is greater than 0.6v cc then slow-decay mode is selected. if the voltage on the pfd input is less than 0.21v cc then fast-decay mode is selected. mixed decay is between these two levels. dwg. wk-004-17 phase 1 current phase 2 current step input slow decay mixed decay slow decay mixed decay 100% ?100% 100% ?100% slow decay mixed decay slow decay mixed decay 38.3% 70.7% ?70.7% 70.7% ?70.7% ?38.3% 38.3% ?38.3%
microstepping driver with translator a3967 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 8 microstep/step operation ms 1 = ms 2 = h, dir = h the mixed-decay mode is controlled by the percent fast decay voltage (v pfd ). if the volt- age at the pfd input is greater than 0.6v cc then slow-decay mode is selected. if the volt- age on the pfd input is less than 0.21v cc then fast-decay mode is selected. mixed decay is between these two levels. dwg. wk-004-16 phase 2 current 100% ?100% slow decay mixed decay slow decay mixed decay phase 1 current step input slow decay mixed decay slow decay mixed decay 100% ?100% 70.7% 38.3% ?70.7% ?38.3% 70.7% 38.3% ?70.7% ?38.3%
microstepping driver with translator a3967 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com terminal list terminal terminal name terminal description number ref gm reference input 1 rc 2 analog input for xed offtime ? bridge 2 2 sleep logic input 3 out 2b h bridge 2 output b 4 load supply 2 v bb2 , the load supply for bridge 2 5 gnd analog and power ground 6, 7 sense 2 sense resistor for bridge 2 8 out 2a h bridge 2 output a 9 step logic input 10 dir logic input 11 ms 1 logic input 12 ms 2 logic input 13 logic supply v cc , the logic supply voltage 14 enable logic input 15 out 1a h bridge 1 output a 16 sense 1 sense resistor for bridge 1 17 gnd analog and power ground 18, 19 load supply 1 v bb1 , the load supply for bridge 1 20 out 1b h bridge 1 output b 21 reset logic input 22 rc 1 analog input for xed offtime ? bridge 1 23 pfd mixed decay setting 24 load supply 1 enable out 1a step out 1b reset sense 1 dir out 2a pfd rc 1 8 logic supply sleep gnd load supply 2 ref rc 2 out 2b ms 2 ms 1 sense 2 pwm timer translator & control logic v bb2 v bb1 v cc dwg. pp-075-2 23 17 8 1 2 3 4 5 6 7 9 12 16 15 14 13 24 22 21 20 19 18 11 10 gnd gnd gnd pin-out diagram
microstepping driver with translator a3967 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com for the latest version of this document, go to our website at: www.allegromicro.com copyright ?2002-2008, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents, including u. s. patent no. 5,684,427, or u.s. pate nts pending allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. 1.27 0.25 b reference pad layout (reference ipc soic127p1030x265-24m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances b 0.20 0.10 0.41 0.10 2.20 0.65 9.60 1.27 2 1 24 a 15.400.20 2.65 max 10.300.33 7.500.10 c seating plane c 0.10 24x for reference only pins 6 and 7, and 18 and 19 internally fused dimensions in millimeters (reference jedec ms-013 ad) dimensions exclusive of mold flash, gate burrs, and dambar protrusions e t d l d fi ti t li di ti ithi li it h a terminal #1 mark area gauge plane seating plane pcb layout reference view 4 4 0.27 +0.07 ?0.06 0.84 +0.44 ?0.43 2 1 24 package lb 24-pin soic

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